華爲韜定律v2性能不下降，芯片面積和功耗降低40%

近日一名微博博主發佈微博傳播

#華爲韜定律芯片實測# 忘了發微博了，補一下。

V2 新的論文信息還是挺多的，解釋了幾個之前不太明確的點。

1⃣首先，散熱：

高功耗電路不參與摺疊，避免高功耗模塊在垂直方向上疊在一起。

Thermal management remains the critical challenge in the LogicFolding architecture. To address this, we employ a thermal-aware partitioning and floorplanning strategies. During the design phase, we deliberately **oid folding high-power circuits and structurally prevent the spatial adjacency of high-power subsystems.

佈局層面避免摺疊高功耗電路，以及結構上阻止高功耗子系統的空間相鄰，說明散熱的問題必然會考慮。

2⃣其次，性能：

在保持麒麟9030 Pro同樣的性能水平前提下，把電壓從1.1V降到0.9V，測出功耗降低41%、功率密度降低5.6%，那麼理論上，同功耗也就會有更高的性能。

3⃣第三，gear ratio

V2專門解釋了爲什麼 gear ratio 接近1是質變節點。

As the vertical interconnect pitch approaches the dimensions of the top metal layer, the nature of the optimization objective undergoes a fundamental transformation. Historically, when the vertical interconnect pitch is much sparser than the top metal pitch, the design space is fundamentally restricted to a discrete optimization problem. Designers manually defined partition boundaries at the macro level, assigning entire functional blocks to specific dies... LogicFolding proposed here is positioned as a continuous optimization problem, in which fine-grained vertical integration enables the design space to be explored at a level of resolution much higher than that of functional blocks, opening the door to globally coordinated optimization of circuits across the vertical dimension.

說的簡單點，那就是從離散優化（模塊級，誰的模塊放哪層）變成連續優化（單元級，每個邏輯門單獨決定放哪層）。

4⃣最後：LogicFolding vs Sequential 3D

這也是直接回應「華爲的方案到底是不是真3D」的部分。

It is worth noting that while sequential 3D integration theoretically offers the ultimate fine-grained device or standard-cell granularity by fabricating device layers sequentially, it currently faces significant manufacturing bottlenecks. Most critically, the lower-layer devices are highly prone to performance degradation due to the strict thermal budget constraints inherent in the sequential fabrication process. As a commercially viable realization, LogicFolding achieves the necessary low gear ratio for continuous optimization by utilizing mature, advanced wafer-to-wafer hybrid bonding.

也就是說華爲選擇的不是理論上粒度最細的路線（Sequential 3D），而是在熱穩定性和粒度精細度之間做了工程權衡，用成熟的W2W HB技術去逼近Sequential 3D的效果。真3D這個詞本身在學術上也有更細的分類，華爲是比較務實的路線。

Figure 3(b) 直接給出了麒麟2026鍵合界面的實拍截面圖，可信度還是非常高的。

麒麟2026和麒麟2027均已完成流片，等新手機就好了。

曝華爲Mate90正在芯片裝測